Design of a low-power D flip-flop for test-per-scan circuits

Power consumption of very large scale integrated (VLSI) systems is much higher during testing as a result of increased circuit activity. This paper presents a novel low-power D flip-flop (DFF) design for test-per-scan circuits. Conventional scannable DFF are modified to ensure that the inputs to the circuit under test (CUT) remain unchanged until an entire test vector is loaded. This eliminates power dissipation in the CUT during scan operation. The proposed design offers an overall 47 % savings in average power compared to previous work in Gerstendorfer et al. (1999) and a 97 % savings in average power and an 8 % peak power savings compared to a conventional DFF.