Title :
Design of a defect-tolerant and fully testable PLA
Author :
Wehn, N. ; Glesner, M. ; Mann, P. ; Caesar, K. ; Roth, A.
Author_Institution :
Inst. fuer Halbleitertech., Tech. Hochschule Darmstadt, West Germany
Abstract :
The authors present a defect-tolerant and fully testable programmable logic array (PLA) that is based on dynamic redundancy, allowing for the repair of a defective chip. Special emphasis is placed on the location of defects inside a PLA. The repair process consists of replacing a defect product term by a programmable spare one.<>
Keywords :
cellular arrays; logic arrays; logic design; logic testing; redundancy; defect-tolerant; defective chip repair; dynamic redundancy; fully testable PLA; programmable logic array; Automatic testing; Circuit faults; Circuit testing; Delay effects; Hardware; Logic design; Microwave integrated circuits; Programmable logic arrays; Redundancy; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo, Finland
DOI :
10.1109/ISCAS.1988.14905
