• DocumentCode
    1606131
  • Title

    An architecture of on-chip-memory multi-threading processor

  • Author

    Matsuzaki, Takanori ; Tomiyasu, Hiroshi ; Amamiya, Makoto

  • Author_Institution
    Dept. of Intelligent Syst., Kyushu Univ., Fukuoka, Japan
  • fYear
    2001
  • fDate
    6/23/1905 12:00:00 AM
  • Firstpage
    100
  • Lastpage
    108
  • Abstract
    This paper proposes an on-chip-memory processor architecture: FUCE. FUCE means Fusion of Communication and Execution. The goal of the FUCE processor project is fusing the intra processor execution and inter processor communication. In order to achieve this goal, the FUCE processor integrates the processor units, memory units and communication units into a chip. FUCE Processor provides a next generation memory system architecture. In this architecture, no data cache memory is required, since memory access latency can be hidden due to the simultaneous multithreading mechanism and the on-chip-memory system with broad-bandwidth low latency internal bus of FUCE Processor. This approach can reduce the performance gap between instruction execution, and memory and network accesses
  • Keywords
    memory architecture; multi-threading; parallel architectures; FUCE; FUCE processor; memory access latency; memory system architecture; multi-threading processor; on-chip-memory processor architecture; Memory architecture;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Innovative Architecture for Future Generation High-Performance Processors and Systems, 2001
  • Conference_Location
    Maui, HI
  • ISSN
    1537-3223
  • Print_ISBN
    0-7695-1309-3
  • Type

    conf

  • DOI
    10.1109/IWIA.2001.955202
  • Filename
    955202