Title :
Automatic logic and timing model generation for cell based design
Author :
Ay, Bulent ; Edelman, R.
Author_Institution :
SimQuest Corp., Santa Clara, CA, USA
Abstract :
A proven methodology for generating and maintaining ASIC libraries automatically, and the software used in implementing this methodology are described. The models generated by this methodology are consistent in terms of functionality, naming, attributes and other characteristics. The models generated by each generator are considered correct by construction, once the operation of the generator is verified. Therefore, functional verification is reduced to a single task of verification of the generator, compared to the verification of each model generated through manual efforts
Keywords :
application specific integrated circuits; circuit CAD; integrated logic circuits; logic CAD; ASIC libraries; all description file; automatic logic generation; cell based design; functional verification; timing model generation; Analytical models; Application specific integrated circuits; Automatic logic units; Computer aided engineering; Hardware design languages; Software libraries; Software maintenance; Switches; Timing; Workstations;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270224
