Reliability Characteristics of TANOS (TaN/AlO/SiN/Oxide/Si)NAND Flash Memory with Rounded Corner (RC) Structure

Author

Chang, Sung-Il ; Lee, Chang-Hyun ; Kang, Changseok ; Jeon, Sanghun ; Kim, Juhyung ; Choi, Byeong-In ; Park, Youngwoo ; Park, Jintaek ; Jeong, Wonseok ; You, Janghyun ; Choi, Bonghyun ; Sel, Jongsun ; Sim, Jae Sung ; Shin, Yoocheol ; Choi, Jungdal ; Lee, W

Author_Institution

Semicond. R&D Center, Samsung Electron. Co., Ltd., Hwasung

fYear

2008

Firstpage

117

Lastpage

118

Abstract

Charge trap flash (CTF) memory is one of the most promising technologies for the next generation NAND technology. Among various CTF memories, excellent manufacturability of TaN-Al₂O₃-Si₃N₄-SiO₂-Si (TANOS) structure has been successfully developed by achieving 32Gb MLC NAND flash using 40nm technology node (Y. Park et al., 2006). 3 dimensional NAND cells such as hemispherical corner (HC) (D. Kwak et al., 2007) and FinFET TANOS (S. Lee et al., 2006) devices with suppressed short-channel effects and improved data retention characteristic were also proposed as cell structures for the next generation beyond 40nm technology node. However, understanding of other device characteristics such as disturb characteristics of the structures is still insufficient. In this paper, various device characteristics of rounded corner (RC) TANOS including disturb and data retention characteristics are investigated and compared with the conventional planar TANOS. Finally, the rendering of RC TANOS for improving disturb characteristics was proposed.

Keywords

NAND circuits; aluminium compounds; flash memories; integrated circuit reliability; silicon compounds; tantalum compounds; MLC NAND flash; TANOS NAND flash memory; TaN-Al₂O₃-Si₃N₄-SiO₂-Si; charge trap flash memory; data retention characteristic; reliability characteristics; rounded corner structure; short-channel effect suppression; size 40 nm; storage capacity 32 Gbit; Electron traps; Electronic mail; FinFETs; Flash memory; Research and development; Semiconductor device manufacture; Semiconductor device reliability; Silicon compounds; Stress; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Non-Volatile Semiconductor Memory Workshop, 2008 and 2008 International Conference on Memory Technology and Design. NVSMW/ICMTD 2008. Joint

Conference_Location

Opio

Print_ISBN

978-1-4244-1546-5

Electronic_ISBN

978-1-4244-1547-2

Type

conf

DOI

10.1109/NVSMW.2008.40

Filename

4531840