A standard cell set for delay insensitive VLSI design

Delay insensitive circuits can solve several problems of VLSI designs. A synthesis system that automatically generates delay insensitive circuits from behavioral specifications has been developed by means of connection of dedicated standard cells. The electrical characterization of the standard cell set is presented, with emphasis on the new aspects introduced by this field of VLSI design. Complexity and speed parameters of each cell are reported. A first example of layout obtained by the system is present and evaluated