DocumentCode
1608671
Title
Design of electronic hardware using VHDL described with the example of baseband and LMP layers in Bluetooth
Author
Costov, Illan Vladimirov ; Filipova, Krassimira
Author_Institution
Tech. Univ., Sofia, Bulgaria
Volume
3
fYear
2004
Firstpage
453
Abstract
Each network device or portable device with HOST interface (radio or cable) has several hierarchical structures which distribute functionality between different layers of that device. Bluetooth is a radio interface which support this architecture. There are five mandatory layers of hierarchy defined: radio interface; baseband layer; link manager protocol (LMP) layer; logical link control and adaptation protocol (L2CAP) layer; HOST user interface. The paper describes the design of the digital baseband and LMP layers from the hardware development aspect of network algorithms. The baseband layer performs the functions related to interface interaction between the Bluetooth chipset and an external or integrated radio chip and a host system. In baseband, different modules for data processing are integrated, like modules for generating frequency hopping sequences, fast error correction codes, cyclic redundancy check algorithm, whitening, data packet assembling and de-assembling. In addition, some hardware optimizations have been made to meet the requirements of modern electronics. By reason of a higher degree of design abstraction, the development of the module has been done with hardware description language $VHDL. During development of the Bluetooth module, a new complex architecture is integrated; it supports low cost upgrades related to new generations of Bluetooth devices. The design has been provided with a generic microprocessor interface for easy adaptation in the Bluetooth system.
Keywords
Bluetooth; circuit optimisation; cyclic redundancy check codes; data communication; digital radio; error correction codes; hardware description languages; modules; network synthesis; packet radio networks; protocols; Bluetooth; VHDL; cyclic redundancy check algorithm; data packet assembling; data packet de-assembling; data transmission; digital baseband layer; electronic hardware design; fast error correction codes; frequency hopping sequence generation; generic microprocessor interface; hardware description language; hardware optimization; interface interaction; link manager protocol layer; logical link control and adaptation protocol layer; radio chip; user interface; whitening; Algorithm design and analysis; Baseband; Bluetooth; Data processing; Frequency; Hardware; Protocols; Radio control; Radio spectrum management; User interfaces;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004. 27th International Spring Seminar on
Print_ISBN
0-7803-8422-9
Type
conf
DOI
10.1109/ISSE.2004.1490855
Filename
1490855
Link To Document