An ETL gate array implementation of a 2.5 Gb/s, 48-bit wide, channel programmable demultiplexer for fiber optic data transmission

Author

Houghten, Jonathan L. ; Prioste, Jerry E.

Author_Institution

Motorola Inc., Chandler, AZ, USA

fYear

1992

Firstpage

91

Lastpage

94

Abstract

Describes unique circuit and logic design techniques in the implementation of a 48-channel programmable demultiplexer using a mature, high-yielding, bipolar ECL gate array for data transmission at 2.5 Gb/s. The new high-frequency macros and the unique design of the timing control circuitry enable a mature process technology to be used to more than double the operating rate of the technology compared to standard methods

Keywords

demultiplexing equipment; emitter-coupled logic; logic arrays; optical communication equipment; optical fibres; transistor-transistor logic; 2.5 Gbit/s; ETL gate array implementation; bipolar ECL gate array; channel programmable demultiplexer; fiber optic data transmission; high-frequency macros; logic design techniques; operating rate; timing control circuitry; Circuits; Clocks; Data communication; Flip-flops; Frequency; Gallium arsenide; Latches; Optical design; Optical fibers; Shift registers;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0768-2

Type

conf

DOI

10.1109/ASIC.1992.270299

Filename

270299