A GaAs ASIC chip set for NASAs deep space network

Author

Graham, J. Scott ; Thompson, Matthew S. ; Johnson, Robert A.

Author_Institution

Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA

fYear

1992

Firstpage

57

Lastpage

63

Abstract

A new GaAs chip set is the core of a new ground-based digital receiver to be installed in NASA´s deep space network. GaAs technology is needed to handle the high-precision carrier demodulation process at the data rate of 160 million samples per second. The chip set architecture and design strategy are discussed. The capabilities of the digital signal processor printed wiring assembly which contains the ASIC chip set are described, together with design verification techniques for the chip set itself

Keywords

III-V semiconductors; application specific integrated circuits; demodulation; digital communication systems; space communication links; ASIC chip set; GaAs; NASA; carrier demodulation process; chip set architecture; deep space network; design strategy; design verification techniques; ground-based digital receiver; printed wiring assembly; Application specific integrated circuits; Automatic testing; Baseband; Circuit testing; Demodulation; Digital signal processing chips; Gallium arsenide; NASA; Signal processing; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0768-2

Type

conf

DOI

10.1109/ASIC.1992.270307

Filename

270307