An efficient implementation of floating point multiplier

Author

Al-Ashrafy, Mohamed ; Salem, Ashraf ; Anis, Wagdy

Author_Institution

Mentor Graphics, Cairo, Egypt

fYear

2011

Firstpage

1

Lastpage

5

Abstract

In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit. With latency of three clock cycles the design achieves 301 MFLOPs. The multiplier was verified against Xilinx floating point multiplier core.

Keywords

adders; field programmable gate arrays; floating point arithmetic; hardware description languages; logic CAD; multiplying circuits; pipeline arithmetic; CAD design flow; IEEE 754 single precision floating point multiplier implementation; MAC unit; MFLOP; VHDL; Xilinx Virtex-5 FPGA; Xilinx floating point multiplier core; adder; multiply-accumulate unit; technology-independent pipelined design; three clock cycles; Adders; Arrays; Clocks; Field programmable gate arrays; Graphics; Logic gates; Pipeline processing; CAD design flow; FPGA; floating point; multiplication;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Communications and Photonics Conference (SIECPC), 2011 Saudi International

Conference_Location

Riyadh

Print_ISBN

978-1-4577-0068-2

Electronic_ISBN

978-1-4577-0067-5

Type

conf

DOI

10.1109/SIECPC.2011.5876905

Filename

5876905