DocumentCode
161097
Title
Improvement of CMOS latch-up in bootstrapping circuit application
Author
Jung-Ruey Tsai ; Yi-Sheng Chang ; Jui-Chang Lin ; Shu-Ming Bai ; Gene Sheu ; Shao-Ming Yang ; Chun-Hsien Wu ; Hsueh-Chun Liao ; Ruey-Dar Chang
Author_Institution
Dept. of Photonic & Commun. Eng., Asia Univ., Taichung, Taiwan
fYear
2014
fDate
7-10 May 2014
Firstpage
1
Lastpage
4
Abstract
This work presents a design guideline for free latch-up in the CMOS inverter caused by shifting time waveform for various device sizes which is demonstrated by 2D TCAD simulations. The design window for improving the CMOS latch-up is investigated by increasing distance anode to cathode of parasitic silicon-controlled-rectifier (SCR) or source to bulk of NMOS.
Keywords
CMOS logic circuits; bootstrap circuits; flip-flops; integrated circuit design; logic design; logic gates; 2D TCAD simulations; CMOS inverter; CMOS latch-up; NMOS; SCR; bootstrapping circuit application; cathode; design window; device sizes; distance anode; parasitic silicon-controlled-rectifier; time waveform; Anodes; CMOS integrated circuits; Educational institutions; Inverters; MOS devices; Semiconductor device modeling; Transistors; CMOS; booststrapping; latch-up;
fLanguage
English
Publisher
ieee
Conference_Titel
Next-Generation Electronics (ISNE), 2014 International Symposium on
Conference_Location
Kwei-Shan
Type
conf
DOI
10.1109/ISNE.2014.6839331
Filename
6839331
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