Title :
Simple and efficient CMOS circuit for fast VLSI adder realization
Author :
Oklobdzija, Vojin G.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
A simple, yet efficient, scheme for a VLSI implementation of addition in CMOS is presented. The implementation of this scheme yields an adder with near minimal number of gates and a small and regular area that outperforms carry-lookahead and recurrence solver schemes. This is demonstrated by simulation of the actual implementation, using examples. The development of this scheme is based on a more realistic estimate of delay in VLSI-CMOS technology and careful selection of circuits than the estimates traditionally used. Using the proposed scheme developed, 32-bit addition in 14.2 ns was realized and, based on it, a 64-bit adder performing addition in 16.0 ns was made possible
Keywords :
CMOS integrated circuits; VLSI; adders; integrated logic circuits; 14.2 ns; 16.0 ns; 32 bits; 64 bits; CMOS circuit; fast VLSI adder realization; gates; minimal number; Adders; Application specific integrated circuits; CMOS technology; Computational modeling; Delay estimation; Libraries; Propagation delay; Semiconductor device modeling; Very large scale integration; Wiring;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo
DOI :
10.1109/ISCAS.1988.14910
