DocumentCode :
1613741
Title :
Syndrome simulation and syndrome test for unscanned interconnects
Author :
Su, Chauchin ; Hwang, Shyh-Shen ; Jou, Shyh-Jye ; Ting, Yuan-Tzu
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
fYear :
1996
Firstpage :
62
Lastpage :
67
Abstract :
In this paper, we present a syndrome test methodology for the testing of unscanned interconnects in a boundary scan environment. Mathematical equations are derived for the relationship of test length, fault-free and faulty syndromes, and tolerable error rate. To calculate fault-free and faulty syndromes, we propose an event driven syndrome simulation algorithm. To shorten testing time and reduce test cost, we transform and solve the problem as a set covering problem
Keywords :
automatic testing; boundary scan testing; built-in self test; circuit analysis computing; discrete event simulation; multichip modules; printed circuit testing; MCM; board level testing; boundary scan environment; event driven syndrome simulation; fault-free syndromes; faulty syndromes; partially scanned PCB; set covering problem; simulation algorithm; syndrome test methodology; test cost reduction; test length; test pattern generation; tolerable error rate; unscanned interconnects; weighted random patterns; Built-in self-test; Circuit faults; Circuit testing; Counting circuits; Integrated circuit interconnections; Monitoring; Random variables; Sequential analysis; Sequential circuits; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 1996., Proceedings of the Fifth Asian
Conference_Location :
Hsinchu
ISSN :
1085-7735
Print_ISBN :
0-8186-7478-4
Type :
conf
DOI :
10.1109/ATS.1996.555138
Filename :
555138
Link To Document :
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