Title :
Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces
Author :
Chang, Wei-Jen ; Ker, Ming-Dou
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Layout optimization on low-voltage-triggered PNP (LVTPNP) devices for ESD protection in mixed-voltage I/O interfaces is proposed in this paper. The experimental results in both 0.35-μm and 0.25-μm CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the original layout style. Moreover, the LVTPNP device in multi-finger layout style has been implemented in a 0.25-μm salicided CMOS process to protect successfully the input stage of an ADSL IC with power-rail ESD clamp circuit.
Keywords :
CMOS integrated circuits; circuit optimisation; digital subscriber lines; electrostatic discharge; integrated circuit interconnections; integrated circuit layout; integrated circuit measurement; low-power electronics; power supply circuits; protection; 0.25 micron; 0.35 micron; ADSL IC input stage; ESD levels; ESD protection; LVTPNP; layout optimization; low-voltage-triggered PNP devices; mixed-voltage I/O interfaces; multi-finger layout style; power-rail ESD clamp circuit; salicided CMOS process; CMOS integrated circuits; CMOS process; Electrostatic discharge; Integrated circuit layout; Laboratories; Nanoelectronics; Power system protection; Robustness; Silicon; Voltage;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the
Print_ISBN :
0-7803-8454-7
DOI :
10.1109/IPFA.2004.1345599
