A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS

ADPLL frequency synthesizers have recently drawn significant research attention as the technology paradigm shifts into the nanometer CMOS arena. They circumvent several design issues that conventional charge-pump-based PLLs encounter, including capacitor leakage, current mismatch, and limited dynamic range. Furthermore, they benefit from replacing the bulky passive loop filter by a more cost-effective and flexible digital filter. The architecture of the presented ADPLL is composed of a dual-mode PFD, a PI digital loop filter composed of programmable integral (alpha) and proportional (beta) paths, a locking process monitor (LPM), an LC-based DCO, a divide-by-4 prescaler, and two phase accumulators PAC1 and PAC2. The PAC1 accumulates quarter of the frequency multiplication factor (N/4) while PAC2 accumulates the prescaler output phase. The phase difference (Phi_E) between f_REF and f_OUT/N is then resolved by a subtractor. The dual-mode PFD is operated in the linear mode during frequency acquisition, and is turned into binary mode during the phase tracking process.