Title :
Numerical characterization of the stress induced voiding inside via of various Cu/low k interconnects
Author :
Yao, C.H. ; Huang, T.C. ; Chi, K.S. ; Wan, W.K. ; Lin, H.H. ; Hsia, Chin C. ; Liang, M.S.
Author_Institution :
Adv. Module Technol. Div., Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan
Abstract :
Modelling methodologies including a dynamic stress evolution are proposed in this work to characterize the relative stress-induced voiding (SIV) probability inside via of various Cu/low k interconnects. Seven patterns being representative of versatile IC design units are selected. It is demonstrated that our modelling approach can serve as a good method identifying the most troublesome layout units to inside-via SIV, and the results aligned well with the experimental data. From our studies, two kinds of layout styles when designed together are found detrimental: (1) the layout units with via(s) subjected to significant upper-metal edge confinement and (2) the one with via close to big vacancy sources.
Keywords :
integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; integrated circuit reliability; thermal stresses; voids (solid); Cu; Cu interconnects; SIV probability; dynamic stress evolution; inside-via SIV; layout styles; low k interconnects; modelling methodologies; numerical characterization; stress induced voiding; upper-metal edge confinement; vacancy sources; versatile IC design; Circuit synthesis; Circuit testing; Geometry; Integrated circuit interconnections; Joining processes; Numerical simulation; Passivation; Thermal resistance; Thermal stresses; Tin;
Conference_Titel :
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International
Print_ISBN :
0-7803-8308-7
DOI :
10.1109/IITC.2004.1345672
