A cost-effective bus-based multiprocessor system

The authors present a new bus structure called the generalized bus interconnection. In this bus structure all the processors and memory modules are partitioned into a number of processor and memory groups. A processor group is connected to each memory group by a set of multiple buses. For a fixed number of buses, this new bus structure can support more processors than the conventional bus structures. The generalized bus interconnection proposed achieves results comparable to those for the partial multiple bus systems but is even more cost-effective. Simulation results show that the generalized bus system is the most cost-effective among all the bus-based systems