Design of power scaleable MD AC in high performance pipelined ADC

Author

Pei, Fei ; Deng, Honghui ; Yin, Yongsheng

Author_Institution

Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China

fYear

2010

Firstpage

108

Lastpage

111

Abstract

A 9-bit, 125MSPS, power scaleable MDAC applied in high performance pipelined ADC in 1.8V supply voltage, 0.18um CMOS process is presented in this paper. The related circuits: a high gain, high unit gain bandwidth operational amplifier with gain boosting, common-mode feedback and bootstrap are proposed. Additionally, when the sampling rate is changed, the power of the whole MDAC can be significantly modulated by setting modulations of bias in op amp with different combinations of current sources. Simulation results in a 0.18um CMOS process indicated that when programmed at 125MSPS, the signal can correctly set up in 2.1ns; MDAC exhibits a spurious free dynamic range (SFDR)of 73.1 dB and a signal-to-noise and distortion ratio(SNDR)of 60.23dB. It consumes 6.8mw when a 62MHz sine signal is fed in.

Keywords

CMOS integrated circuits; analogue-digital conversion; bootstrap circuits; integrated circuit design; operational amplifiers; pipeline arithmetic; CMOS process; bandwidth operational amplifier; bootstrap; common-mode feedback; gain boosting; high performance pipelined ADC; power scaleable MD AC; size 0.18 mum; Bandwidth; Logic gates; MOS devices; Modulation; Operational amplifiers; Switches; MDAC; bias; pipeline; power modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Anti-Counterfeiting Security and Identification in Communication (ASID), 2010 International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-6731-0

Type

conf

DOI

10.1109/ICASID.2010.5551522

Filename

5551522