Author :
Amamiya, Y. ; Kaeriyama, S. ; Noguchi, H. ; Yamazaki, Z. ; Yamase, T. ; Hosoya, K. ; Okamoto, M. ; Tomari, S. ; Yamaguchi, H. ; Shoda, H. ; Ikeda, H. ; Tanaka, S. ; Takahashi, T. ; Ohhira, R. ; Noda, A. ; Hijioka, K. ; Tanabe, A. ; Fujita, S. ; Kawahara,
Abstract :
In this paper, 40 Gb/s SFI-5-compliant TX and RX chips in 65 nm CMOS technology consume 2.8 W each. This low power dissipation allows for a small and low-cost plastic BGA package. The TX has a full-rate clock architecture that is based on a 40 GHz VCO, a 40 Gb/s retiming D-FF, and 40 GHz clock-distribution circuits that lead to a low jitter of 0.57 psrms and 3.1 pspp at 40 Gb/s. A 40/20 GHz clock-timing-adjustment circuit based on a phase interpolator is used to ensure wide-range error-free operations (BER < 101Z) at 39.8 to 44.6 Gb/s. A quadruple loop architecture is introduced in the CDR circuit of the RX, resulting in a 38 Gb/s error-free operation (BER < 101Z) at 231-1 PRBS with a low rms jitter of 210 fs in the recovered clock.
Keywords :
CMOS integrated circuits; ball grid arrays; field effect MIMIC; integrated optoelectronics; jitter; low-power electronics; millimetre wave oscillators; optical receivers; optical transmitters; voltage-controlled oscillators; SFI-5 interface; VCO; bit rate 40 Gbit/s; clock-timing-adjustment circuit; frequency 39.8 GHz to 44.6 GHz; frequency 40 GHz; full-rate clock architecture; jitter; low-power dissipation; multidata-rate CMOS transceiver chipset; optical transmission systems; phase interpolator; plastic BGA package; power 2.8 W; size 65 nm; Bit error rate; CMOS technology; Circuits; Clocks; Error-free operation; Jitter; Plastic packaging; Power dissipation; Transceivers; Voltage-controlled oscillators;
