BLACK/CLAD: a layout synthesis tool for combinational blocks from behavioral HDL descriptions

The first of two loosely coupled CAD tools is presented. BLACK is a synthesis program which generates a topological transistor netlist from a behavioral description written in VHDL, Verilog, truth lab, or Boolean equations. The netlist produced by BLACK is then used by the second tool to produce full custom layouts. The second tool, CLAD, is a layout program which uses simulated annealing to optimize the placement of the different transistor groups. The BLACK and CLAD synthesis system accepts behavioral hardware description language descriptions or transistor netlists as inputs, and generates full-custom two-dimensional layouts rather than standard cell netlists. An example of synthesizing a Muller C, an asynchronous sequential circuit, is given