Title :
21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber
Author :
Cao, Jun ; Zhang, Bo ; Singh, Ullas ; Cui, Delong ; Vasani, Anand ; Garg, Adesh ; Zhang, Wei ; Kocaman, Namik ; Pi, Deyi ; Raghavan, Bharath ; Pan, Hui ; Fujimori, Ichiro ; Momtaz, Afshin
Author_Institution :
Broadcom, Irvine, CA
Abstract :
The demand for bandwidth has fueled the deployment of 10 Gb/s traffic over legacy data links such as serial backplanes (10GBase-KR) and multimode fiber (10 GBase-MMF) which were originally intended for much lower data rates. Under severe channel impairments, a DSP-based transceiver provides robust performance and enables power/area scaling with processes. This work describes a 65 nm CMOS AFE integrated in a DSP-based PHY for 10 Gb/s KR/MMF applications.
Keywords :
CMOS digital integrated circuits; calibration; digital signal processing chips; CMOS; CMOS AFE; DSP-based transceiver; KR-MMF applications; backplane-multimode fiber; bit rate 10 Gbit/s; digitally calibrated AFE; legacy data links; power-area scaling; Backplanes; Bandwidth; Clocks; Flip-flops; Frequency; Jitter; Phase detection; Phase noise; Solid state circuits; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977462
