• DocumentCode
    1618330
  • Title

    An 8-bit 22-MHz recycling two-step ASIC ADC with integrating sample and hold

  • Author

    Wongkittikriwon, Somsak ; Burns, Stanley G.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
  • fYear
    1992
  • Firstpage
    839
  • Abstract
    A recycling two-step architecture with a very low input current comparator is presented to implement an 8-b analog-to-digital converter (ADC) with an integrating sample and hold circuit that yields a 22-Msps conversion rate with a 10-MHz input. This two-step recycling architecture makes use of a novel switch circuit design reducing the number of components required for the complete ADC. The ADC is realized using 900 transistors on two-metal, fT=8.5 GHz, npn bipolar junction transistor (BJT) application-specific integrated circuits
  • Keywords
    analogue-digital conversion; application specific integrated circuits; bipolar integrated circuits; comparators (circuits); sample and hold circuits; bipolar ICs; comparator; conversion rate; input current; integrating sample and hold; recycling two-step ASIC ADC; switch circuit design; Algorithm design and analysis; Application specific integrated circuits; Circuits and systems; Clocks; Integrated circuit technology; Latches; Recycling; Samarium; Switches; Switching circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
  • Conference_Location
    Washington, DC
  • Print_ISBN
    0-7803-0510-8
  • Type

    conf

  • DOI
    10.1109/MWSCAS.1992.271193
  • Filename
    271193
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1618330