Emitter injection control in LVTSCR for latch-up free ESD protection

Author

Vashchenko, V. ; Concannon, A. ; Beek, M. Ter ; Hopper, P.

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

Volume

2

fYear

2002

fDate

6/24/1905 12:00:00 AM

Firstpage

741

Lastpage

744

Abstract

A low-voltage triggered silicon controlled rectifier with optimized holding voltage for ESD protection, has been developed and is demonstrated in a 0.18 μm CMOS technology. Process and device simulation is used to determine the relationship between electrical parameters and geometrical features. Pulse measurements of silicon test structures demonstrate that the ESD efficiency of this approach is 3-5 times that of a conventional grounded gate snapback n-MOS with the same holding voltage

Keywords

CMOS integrated circuits; electrostatic discharge; protection; pulse measurement; semiconductor device measurement; semiconductor device models; semiconductor process modelling; thyristors; 0.18 micron; CMOS technology; ESD efficiency; LVTSCR; device simulation; electrical parameters; emitter injection control; geometrical features; holding voltage; latch-up free ESD protection; low-voltage triggered silicon controlled rectifier; process simulation; pulse measurements; silicon test structures; Biological system modeling; CMOS technology; Circuit simulation; Electrostatic discharge; Equations; Latches; Protection; Space charge; Thyristors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2002. MIEL 2002. 23rd International Conference on

Conference_Location

Nis

Print_ISBN

0-7803-7235-2

Type

conf

DOI

10.1109/MIEL.2002.1003363

Filename

1003363