Guest editorial - Design methodologies for nanoelectronic digital and analogue circuits

Mobile computing systems, multimedia content players and medical electronics are some of the applications that are driving strong growth in VLSI technology. Although the nanoscale CMOS Field Effect Transistor (FET) is going strong with room for further scaling, other nanoelectronics technologies like Multigate FET, Graphene FET, Tunnel FET, are being researched widely as possible successors. Though the key issues in design such as managing power consumption, leakage, thermal effects, process variation, reliability and security remain the same, newer technologies provide additional levers to address those problems. However, integrating new solutions with current methodologies, whereas producing robust and efficient chips with both high-design productivity and manufacturing yield remains a challenge. With this context in mind, the Special Issue on ´esign Methodologies for Nanoelectronic Digital and Analog Circuits´ has been brought to serve VLSI researchers and design engineers.