Title :
ESD-transient detection circuit with equivalent capacitance-coupling detection mechanism and high efficiency of layout area in a 65nm CMOS technology
Author :
Chih-Ting Yeh ; Ming-Dou Ker
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
A new power-rail ESD clamp circuit designed with equivalent capacitance-coupling detection mechanism and high efficiency of layout area has been proposed and verified in a 65nm 1.2V CMOS process. The proposed design has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of the proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit by both reducing ~46%.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit layout; leakage currents; CMOS process; CMOS technology; RC-based power-rail ESD clamp circuit; size 65 nm; standby leakage current; transient-induced latch-on event; voltage 1.2 V; Capacitance; Clamps; Current measurement; Electrostatic discharges; Layout; Leakage currents; Transmission line measurements;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2013 35th
Conference_Location :
Las Vegas, NV
