F6: Multi-domain processors

Multiple clock and power domains are widely used to manage power in modern nanoscale designs. This Forum will present the latest design techniques in multiple-domain clock and power management for high-performance processors, as well as low-power systems-on-chip (SoC). Topics include clock and data synchronization, power gating, floorplan and layout implications, clock and power grids, test requirements, modular design techniques. Practical examples will be presented from both industry and academia.