Title :
An efficient full-chip ESD paths resistance value verification flow for large scale designs
Author :
Meng-Fan Wu ; Chun-Chien Tsai ; Jen-Chou Tseng ; Chao, Roger ; Ming-Hsiang Song ; Yi-Kan Cheng
Author_Institution :
Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan
Abstract :
Commercial EDA tools are available to verify resistance values of ESD paths. However, since ESD paths relate to whole-chip power/ground (P/G) nets, state-of-the-art commercial resistance extraction tools may result in memory overflow issues when the complexity of P/G nets is too high. The latest 28 nm real products exhibit such issues. This paper presents an efficient flow which solves this issue.
Keywords :
circuit complexity; electric resistance; electrostatic discharge; power semiconductor devices; P/G nets complexity; commercial EDA tools; commercial resistance extraction tools; full-chip ESD paths resistance value verification flow; large scale designs; memory overflow; size 28 nm; whole-chip power/ground nets; Electrostatic discharges; Immune system; Integrated circuit interconnections; Layout; Metals; Resistance; Runtime;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2013 35th
Conference_Location :
Las Vegas, NV
