An efficient full-chip ESD paths resistance value verification flow for large scale designs

Commercial EDA tools are available to verify resistance values of ESD paths. However, since ESD paths relate to whole-chip power/ground (P/G) nets, state-of-the-art commercial resistance extraction tools may result in memory overflow issues when the complexity of P/G nets is too high. The latest 28 nm real products exhibit such issues. This paper presents an efficient flow which solves this issue.