Title :
Stack-transistor based differential 8T SRAM cell for embedded memory applications
Author :
Weijie Cheng ; Baolong Zhou ; Huarong Zheng ; Yeonbae Chung
Author_Institution :
Sch. of Electron. Eng., Kyungpook Nat. Univ., Daegu, South Korea
Abstract :
In this work, we present a novel 8T SRAM cell that enhances the stability of built-in data storage elements. During a read operation, the proposed cell suppresses a noise-vulnerable `0´ node rising, and hence exhibiting near-ideal butterfly curve essential for robust SRAM bit-cell design. The cell itself bears an improved variability tolerance which gives much tight stability distribution across skewed process corners. Implementation results in a 130 nm CMOS technology show that the 8T cell achieves almost 100 % higher read stability compared to the standard 6T cell. The data write-ability and stability tolerance provided with the new cell are also verified under process and temperature variations.
Keywords :
CMOS memory circuits; SRAM chips; circuit stability; embedded systems; integrated circuit design; 6T cell; CMOS technology; SRAM bit-cell design; built-in data storage element; data write-ability; embedded memory application; process variation; read operation; read stability; size 130 nm; skewed process; stability distribution; stability tolerance; stack-transistor based differential 8T SRAM cell; temperature variation; variability tolerance; CMOS integrated circuits; CMOS technology; Inverters; SRAM cells; Thermal stability; Transistors; 8T cell; SRAM; data stability; embedded memory;
Conference_Titel :
Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on
Conference_Location :
Bangkok
Print_ISBN :
978-1-4673-5694-7
DOI :
10.1109/EDSSC.2012.6482890
