DocumentCode
1620549
Title
9-valued 2-dimensional parallel switch level fault simulation
Author
Ryan, Christopher A. ; Tront, Joseph G.
Author_Institution
Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
fYear
1992
Firstpage
348
Abstract
Switch level fault simulation increases accuracy over gate level fault simulation at the cost of increased complexity. A two-dimensional extension to parallel fault simulation for the switch level is presented. Using 9-valued logic and a parallel hardware accelerated fault simulator, simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input
Keywords
circuit analysis computing; logic CAD; logic testing; many-valued logics; 9-valued logic; parallel fault simulation; parallel hardware accelerated fault simulator; simulation complexity; switch level fault simulation; two-dimensional extension; Acceleration; Circuit faults; Circuit simulation; Computational modeling; Degradation; Hardware; Logic; Switches; Switching circuits; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
Conference_Location
Washington, DC
Print_ISBN
0-7803-0510-8
Type
conf
DOI
10.1109/MWSCAS.1992.271289
Filename
271289
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