Title :
A pipelined VLSI arithmetic architecture
Author :
Zhang, D. ; Jullien, G. ; Miller, W. ; Elmasry, M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Abstract :
A pipelined VLSI arithmetic architecture (PVAA), based on binary trees drawn from truth tables and matched to a dynamic logic cell (DLC), is presented. The modeling height reduction and multioutput logic of a DLC are discussed. Two typical switching tree structures, layered tree and sub-tree are developed. The latter covers three types of designs, i.e., serial, parallel, and pyramid. Several examples for different applications are given, and simulation results are obtained to illustrate the effectiveness of the PVAA
Keywords :
CMOS integrated circuits; VLSI; adders; digital arithmetic; integrated logic circuits; parallel architectures; pipeline processing; trees (mathematics); CMOS; adders; binary trees; comparators; dynamic logic cell; layered tree; modeling height reduction; multioutput logic; multipliers; parallel structure; pipelined VLSI arithmetic architecture; pyramid structure; serial structure; simulation; sub-tree; switching tree structures; truth tables; Application software; Arithmetic; Binary trees; Buildings; CMOS logic circuits; Computer architecture; Logic design; MOSFETs; Switches; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-0510-8
DOI :
10.1109/MWSCAS.1992.271293
