Binary division algorithm and high speed deconvolution algorithm (Based on Ancient Indian Vedic Mathematics)

The performance of any processor solely depends upon its power, area and delay. In order to get an effective processor, its power, area and delay should be less. Division is always considered to be bulky and one of the most difficult operations in arithmetic and hence all the implementations of division algorithms in VLSI architecture have higher orders of time and space complexities. Vedic Mathematics on the other hand offers a new holistic approach to mathematics. Its range extends from the most concrete values of numerical computation to the most abstract aspects of the dynamics of intelligence. In this work we have implemented an optimized binary division architecture using sutras of Vedic Mathematics which are Nikhilam Sutra and Parvartya Sutra. This work discusses about these two algorithms of division and their application for calculating deconvolution. Both the algorithms have been implemented with improved results of time delay and are with fewer complexities. The proposed division algorithm is coded in Verilog, synthesized and simulated using Xilinx ISE design suit 14.2. Simulated results for proposed Vedic divider circuit shows a reduction in delay of 19% than the conventional method.