DocumentCode :
1622192
Title :
Capacity Planning Method for Semiconductor Fab with Time Constraints between Operations
Author :
Kitamura, Shoichi ; Mori, Kazuyuki ; Ono, Akira
Author_Institution :
Adv. Technol. R&D Center, Mitsubishi Electr. Corp., Hyogo
fYear :
2006
Firstpage :
1100
Lastpage :
1103
Abstract :
It is difficult to plan capacities of a semiconductor wafer fabrication with constraints of queue time which means a waiting time from the end of a step to the start of the next step for warranting production quality. If the queue time constraints could not be kept, the product is scrapped or reprocessed for qualitative recovery, and production efficiency remarkably decreases. This paper proposes an evaluation method which enables capacity planning of a fab with the queue time constraints, and shows its validity by simulation experiments. Furthermore we present an effectiveness of the method by applying to actual production lines
Keywords :
capacity planning (manufacturing); queueing theory; semiconductor device manufacture; capacity planning method; queuing theory; risk based planning; semiconductor wafer fabrication; Capacity planning; Fabrication; Investments; Manufacturing; Production systems; Queueing analysis; Research and development; Tellurium; Time factors; Upper bound; Capacity planning; queue time; queuing theory; risk based planning; semiconductor fabrication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SICE-ICASE, 2006. International Joint Conference
Conference_Location :
Busan
Print_ISBN :
89-950038-4-7
Electronic_ISBN :
89-950038-5-5
Type :
conf
DOI :
10.1109/SICE.2006.315820
Filename :
4109123
Link To Document :
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