• DocumentCode
    1623409
  • Title

    Neural networks implementation with VLSI

  • Author

    Georges, E.M. ; Lai, L.L. ; Ndeh-Che, F. ; Braun, H.

  • Author_Institution
    City Univ., London, UK
  • fYear
    1995
  • Firstpage
    489
  • Lastpage
    494
  • Abstract
    This paper presents the design of a new and efficient winner-take-all (WTA) cell for the self-organising mapping (SOM) neuron. This cell is implemented in VLSI that provides both faster operation and a reduction in the number of transistors per cell compared to existing designs. The operation of the circuit is described and results of SPICE simulations are presented
  • Keywords
    SPICE; VLSI; analogue integrated circuits; circuit analysis computing; digital simulation; neural chips; self-organising feature maps; transistors; SPICE simulations; VLSI neural network implementation; circuit operation; self-organising mapping neuron; transistors; winner-take-all cell design;
  • fLanguage
    English
  • Publisher
    iet
  • Conference_Titel
    Artificial Neural Networks, 1995., Fourth International Conference on
  • Conference_Location
    Cambridge
  • Print_ISBN
    0-85296-641-5
  • Type

    conf

  • DOI
    10.1049/cp:19950605
  • Filename
    497868
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1623409