Multi-Objective Genetic optimized multiprocessor SoC design

In this paper, we introduce a new multi-objective genetic algorithm (MOGA) for mapping a given set of intellectual property onto a network-on-chip architecture such that for a specific application total communication cost and energy consumption become optimized while bandwidth constraints are satisfied. As the main theoretical contribution, we first introduce a generic queuing model to estimate performance and an experimental energy consumption model during the design phase, with acceptable accuracy. Then, an efficient genetic algorithm employs these models to propose a Pareto optimal front for an application and an arbitrary topology. Experimental results show that the proposed algorithm is very fast which results in a new approach for mapping MPSoC cores on chip.