Title :
High-temperature effects on device performance of a junctionless transistor
Author :
Baruah, Ratul Kumar ; Paily, Roy P.
Author_Institution :
Dept. of Electron. & Electr. Eng., Indian Inst. of Technol., Guwahati, Guwahati, India
Abstract :
This paper presents the effects of high-temperature on the major digital and analog performance parameters of a 20-nm channel length n-type symmetric double-gate junctionless transistor (DGJLT) with the help of extensive device simulations. The characteristics are compared with conventional inversion mode counterpart i.e., double-gate transistor (DGMOS) of same dimension. It is found that the ON-state current increases very marginally with increase in temperature for DGJLT unlike DGMOS in which it decreases. The drain current with respect to drain voltage increases negligibly with increase in temperature for DGJLT, whereas it decreases for DGMOS. Intrinsic gain is almost independent of temperature at higher gate voltage (> 0.6 V) for DGJLT.
Keywords :
MOSFET; semiconductor device testing; ON-state current; device performance; drain current; drain voltage; high-temperature effects; intrinsic gain; n-type symmetric double-gate junctionless transistor; size 20 nm; MOSFET circuits; Radio access networks; High-temperature; Unity gain cut-off frequency; intrinsic gain; junctionless transistor (JLT); subthreshold slope;
Conference_Titel :
Emerging Electronics (ICEE), 2012 International Conference on
Conference_Location :
Mumbai
Print_ISBN :
978-1-4673-3135-7
DOI :
10.1109/ICEmElec.2012.6636273