DocumentCode :
1626396
Title :
Panel: SoC power management implications on validation and testing
Author :
Kapoor, Bhanu ; Goodenough, John ; Hemmady, Shankar ; Verma, Shireesh ; d´Abreu, Manuel A. ; Roy, Kaushik
Author_Institution :
Mimasic, USA
fYear :
2008
Firstpage :
135
Lastpage :
137
Abstract :
We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market towards handheld consumer devices. Power is a primary design criterion for bulk of the semiconductor designs now. Power is a key reason behind the shift towards multi-core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.
Keywords :
Computer science; Delay; Design engineering; Dynamic voltage scaling; Energy consumption; Energy management; Engineering profession; Power engineering and energy; Power supplies; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Level Design Validation and Test Workshop, 2008. HLDVT '08. IEEE International
Conference_Location :
Incline Village, NV, USA
ISSN :
1552-6674
Print_ISBN :
978-1-4244-2922-6
Type :
conf
DOI :
10.1109/HLDVT.2008.4695890
Filename :
4695890
Link To Document :
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