Radix-2h online floating point multipliers

Digital signal processing hardware uses digit serial arithmetic when latency can be traded off for higher clock speeds, resource and input-output utilization. Floating-point representations are important when dealing with very large data sets or sets where data range may be unpredictable as these representations may have a larger dynamic range. Field Programmable Gate Array architectures make them suitable as hardware accelerators for implementing high performance floating-point computations. In this paper, a number of improved designs for Radix-2^h online floating-point multiplication are presented, analysed and compared on the basis of latency, throughput, cycle time and resource utilization. The architecture of a novel online floating-point multiplier using an interleaved number representation that results in an increased throughput and has the advantage of carrying out normalization for overflow with reduction in cycle time, resource utilization and latency is also presented.