Title :
Timing optimization for deep sub-micron hierarchical design
Author :
Xu, Shu-Xin ; Dong, Li-Min ; Peng, Xiao-Hong
Author_Institution :
VLSI & Syst. Lab., Beijing Univ. of Technol., Beijing, China
Abstract :
In this paper, we use design planning method to partition a flat design based on SAED 90 nm process technology into blocks and created interface logic models (ILMs) for each blocks. Using the hierarchical design including ILM, the runtime of the place optimization stage, clock optimization stage and route optimization stage is reduced to 28.8%, 27.7% and 43% relatively, meanwhile the boundary timing become more optimal which can also prove the timing accuracy of ILM.
Keywords :
circuit optimisation; integrated circuit design; timing; clock optimization stage; deep sub-micron hierarchical design; interface logic models; place optimization stage; route optimization stage; size 90 nm; timing optimization; Clocks; Integrated circuit modeling; Optimization; Planning; Runtime; Timing;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667313
