A 200 MHz 6-bit folding and interpolating ADC in 0.5-μm CMOS

Author

Jiang, Xicheng ; Wang, Yunti ; Willson, Alan N., Jr.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

1

fYear

1998

Firstpage

5

Abstract

This paper presents the detailed design of a 200 MHz CMOS ADC with a folding and interpolating architecture. To overcome the input-frequency-multiplication problem inherent in such architectures, a front-end sample/hold circuit is used. The fully differential signal is folded by a factor of five and followed by a four-times interpolation. A double-averaging technique is explored and, with this technique, the analog folding stage can achieve approximately 12-bit linearity. To suppress the misalignment error, a bit alignment circuit is designed. The prototype chip includes about 1400 components and the active chip area is 0.4 mm². Its power consumption is approximately 150 mW at a 200 MHz sampling rate

Keywords

CMOS integrated circuits; analogue-digital conversion; interpolation; sample and hold circuits; 0.5 micron; 150 mW; 200 MHz; 6 to 12 bit; CMOS; active chip area; bit alignment circuit; double-averaging technique; folding ADC; front-end sample/hold circuit; fully differential signal; input-frequency-multiplication problem; interpolating ADC; linearity; misalignment error; power consumption; sampling rate; CMOS integrated circuits; CMOS technology; Digital circuits; Ethernet networks; Frequency conversion; Integrated circuit technology; Interpolation; Power dissipation; Sampling methods; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.704121

Filename

704121