Vector compaction for efficient simulation-based power estimation [CMOS design]

Low power digital CMOS circuit design requires accurate power estimation. To achieve the accuracy of dynamic power estimation and the speed of static estimation methods, one approach is to generate a compact, representative vector set with similar switching behaviour to the original larger vector set. In this paper, we present an algorithm based on fractal concepts to generate a compacted vector that allows fast, accurate power estimation through simulation. The fractal approach exploits the correlation in the toggle distribution of the circuit´s internal nodes for compaction of the input vector set. Experiments on ISCAS85 benchmark circuits with a vector set size of 4000, resulted in a compaction of 65.57× (max) and 38.14× (avg) with power estimation error of 2.40% (max) and 2.06% (avg). Also, experiments with different vector set sizes up to 100,000 were also carried out