• DocumentCode
    1630656
  • Title

    MOSRA: An efficient and versatile MOS aging modeling and reliability analysis solution for 45nm and below

  • Author

    Tudor, Bogdan ; Wang, Joddy ; Sun, Charly ; Chen, Zhaoping ; Liao, Zhijia ; Tan, Robin ; Liu, Weidong ; Lee, Frank

  • Author_Institution
    Synopsys, Inc., Mountain View, CA, USA
  • fYear
    2010
  • Firstpage
    1645
  • Lastpage
    1647
  • Abstract
    MOS device aging caused by hot-carrier injection (HCI) and negative/positive bias-temperature instability (N/PBTI) is increasingly more responsible for IC reliability failure for advanced process technology nodes. Accurate aging modeling and fast yet trustable reliability signoff are thus mandatory in process development and circuit design. This paper will first present an aging model that takes into account accurately those aging mechanisms and is silicon proven for various processes down to 32/28nm. The model formulation on bias, geometry and temperature and, in particular, a unique methodology for modeling the AC partial-recovery effect of BTI is detailed and analyzed. It will then demonstrate an efficient SPICE simulation analysis flow that incorporates this model as well as many and any custom aging models developed by foundries and design houses. Both the model and the simulation flow make an efficient and versatile MOS reliability and analysis solution (MOSRA) that has been used successfully in numerous tapeouts and silicon debugging for 45nm and below.
  • Keywords
    MIS devices; MOS integrated circuits; hot carriers; integrated circuit reliability; AC partial-recovery effect; IC reliability failure; MOS device aging; MOS reliability and analysis solution; SPICE simulation analysis flow; advanced process technology nodes; circuit design; hot-carrier injection; negative-positive bias-temperature instability; process development; silicon debugging; size 45 nm; Aging; Analytical models; Computational modeling; Degradation; Human computer interaction; Integrated circuit modeling; Mathematical model;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-5797-7
  • Type

    conf

  • DOI
    10.1109/ICSICT.2010.5667399
  • Filename
    5667399