Title :
Architecture of the 2B1Q symbol receiver in the MC145472 ISDN U transceiver
Author :
Bonet, Luis A. ; McCaslin, S.R. ; Kuenast, Walter U. ; Williams, Tim A. ; Aly, Sami ; Sayar, Babak ; Hung, Paul ; Bahgat, Ouma ; Deczky, Andrew
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
Motorola and BNR are currently developing the MC145472, a single-chip implementation of an ISDN U reference point, 2B1Q transceiver which conforms to the T1E1 ANSI standard, T1.601. The authors describe the architecture of the portion of the chip that implements the symbol receiver function. The LMS pipe coprocessor and the MEC coprocessor are discussed. A typical execution sequence is also described. It is shown that the processors constituting the symbol receiver enable the U transceiver to recover the 2B1Q symbols and receive clock from the highly distorted receive signal stream. The implementation allows for high processing throughput and maximum flexibility while displacing minimum die area
Keywords :
ISDN; computerised signal processing; data communication equipment; digital signal processing chips; microcomputer applications; satellite computers; telecommunications computing; transceivers; 2B1Q symbol receiver; 2B1Q symbol-recovery; 2B1Q transceiver; BNR; ISDN U reference point; LMS pipe coprocessor; MC145472 ISDN U transceiver; MEC coprocessor; Motorola; T1.601; T1E1 ANSI standard; adaptive echo cancellation; architecture; equalisation; execution sequence; high processing throughput; highly distorted receive signal stream; signal quantisation; single-chip implementation; symbol receiver function; Algorithms; Central Processing Unit; Clocks; Coprocessors; Coupling circuits; Echo cancellers; ISDN; Least squares approximation; Quantization; Transceivers;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100427