DocumentCode :
1631529
Title :
A test generation procedure for avoiding the detection of functionally redundant transition faults
Author :
Lee, Hangkyu ; Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN
fYear :
2006
Lastpage :
299
Abstract :
We present a test generation procedure for transition faults that minimizes the detection of functionally redundant transition faults in scan circuits. The procedure uses broadside testing. We also propose rules for identifying dominance relations between functionally redundant transition faults and functionally detectable transition faults. Dominance relations can provide two types of lower bounds. (1) A lower bound on the number of functionally detectable transition faults that cannot be detected without detecting any functionally redundant transition faults. (2) A lower bound on the number of functionally redundant faults that have to be detected if all the functionally detectable faults are detected. In our experiments with ISCAS-89 and ITC-99 benchmark circuits we achieve both of the lower bounds for almost all the circuits considered
Keywords :
automatic test pattern generation; benchmark testing; fault location; semiconductor device testing; ISCAS-89 benchmark circuit; ITC-99 benchmark circuit; broadside testing; dominance relations; functionally detectable transition fault; functionally redundant transition faults; scan circuits; test generation procedure; Benchmark testing; Circuit faults; Circuit testing; Cities and towns; Clocks; Delay; Electrical fault detection; Fault detection; Fault diagnosis; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2006. Proceedings. 24th IEEE
Conference_Location :
Berkeley, CA
Print_ISBN :
0-7695-2514-8
Type :
conf
DOI :
10.1109/VTS.2006.13
Filename :
1617607
Link To Document :
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