Title :
A testability strategy for silicon compilers
Author :
Beenker, Frans ; Dekker, Rob ; Stans, Rudi ; Van Der Star, Max
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
The authors present a testability strategy for complex VLSI devices which is implemented in the PIRAMID Digital Signal Processor Silicon Compiler. The macrotest methodology supports built-in self-test, scan test, bus test control, restricted partial scan and test control logic at various levels in the design hierarchy. A set of testability design rules is developed and implemented automatically in the design. The design hierarchy is closely followed, resulting in a hierarchical set of testable macros. The complete process from design to final test program is guided by software tools. As an example, the synthesis of a large industrial circuit is presented for comparing the proposed approach with the traditional approaches. The additional overhead due to testability is within reasonable limits (roughly 8%), and the software run time figures show that it is possible to generate a test program with an excellent fault coverage within a very short period of time
Keywords :
VLSI; automatic testing; circuit layout CAD; digital signal processing chips; integrated circuit testing; IC testing; PIRAMID Digital Signal Processor Silicon Compiler; automatic testing; built-in self-test; bus test control; complex VLSI devices; fault coverage; hierarchical set; industrial circuit; macrotest; restricted partial scan; scan test; software tools; test control logic; testability; testable macros; Automatic control; Automatic testing; Built-in self-test; Circuit testing; Digital signal processors; Logic devices; Logic testing; Silicon compiler; Software testing; Very large scale integration;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82353