Title :
Fault tolerance design of VLSI two dimension systolic processor array
Author :
Tong, Q.-Y. ; Liu, Wen-Hao
Abstract :
After briefly reviewing the development of the IC, the authors point out the necessity of introducing fault tolerance techniques to IC design. They discuss two fundamental fault tolerance design techniques for two-dimensional systolic array: direct reconfiguration and a fault-stealing algorithm. The authors propose a reconfiguration method which is easier and more successful than that given by M.G. Sami and R. Steffnelli (see Proc. 1984 Real-Time System Symp., IEEE, Austin)
Keywords :
VLSI; cellular arrays; fault tolerant computing; parallel architectures; 2D VLSI systolic processor array; direct reconfiguration; fault tolerant design; fault-stealing algorithm; reconfiguration; Circuit faults; Costs; Fault tolerance; Fault tolerant systems; Integrated circuit reliability; Manufacturing; Microelectronics; Redundancy; Systolic arrays; Very large scale integration;
Conference_Titel :
Computers and Communications, 1988. Conference Proceedings., Seventh Annual International Phoenix Conference on
Conference_Location :
Scottsdale, AZ
Print_ISBN :
0-8186-0830-7
DOI :
10.1109/PCCC.1988.10043
