Low cost fault detector guided by permanent faults at the end of FPGAs life cycle

Field Programmable Gate Arrays (FPGAs), as any other electronic devices, are designed according to some life expectancy figures. For this reason, its lifetime is finite given due to appearance of faults caused by the natural physical degradation. In this paper, we present a low cost solution for autonomous detection of faults at the end of FPGAs life cycle. Our proposed methodology starts from a pre-analysis of memory elements belonging to modules under verification. Then, with a proper organization, it is created a list of all memory elements, controlled through a Built-In Self-Test (BIST) implementation via the FPGAs Internal Configuration Access Port (ICAP). By means of this list, a virtual scan chain is created, where the vectors (test and result) are written and read using the FPGA reconfiguration capabilities, which means there is no extra hardware to create the physical scan chain. The detection algorithm is implemented in the available system processing unit. The results show that with a minor increase in the program memory of the digital design, it is possible to perform an offline hardware testing of each sub-module in the existing FPGA, with no need of stopping the remaining of the system.