DocumentCode
1637992
Title
A sub-sampling 3-bit 4GS/s flash ADC in 0.13-µm CMOS
Author
Zhao, Yi ; Wang, Shenjie ; Qin, Yajie ; Hong, Zhiliang
Author_Institution
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear
2010
Firstpage
436
Lastpage
438
Abstract
A low-power single-channel sub-sampling 3-bit 4GS/s flash ADC in 0.13-μm CMOS is presented. Resistive averaging network and multi-stage interpolation technique are introduced for offset cancellation and power reduction, respectively. The comparator uses CML (current mode logic) blocks and pipelined structure to further enhance the speed of ADC. The simulation results reveal that the ENOB is 2.9 bit and ERBW is 4.8GHz. The ADC achieves a figure of merit of 0.58pJ/conversion-step.
Keywords
CMOS logic circuits; analogue-digital conversion; comparators (circuits); interpolation; CML; CMOS; ENOB; ERBW; comparator; current mode logic blocks; figure of merit; flash ADC; low-power single-channel sub-sampling; multistage interpolation technique; offset cancellation; pipelined structure; power reduction; resistive averaging network; size 0.13 mum; word length 3 bit; Arrays; Clocks; Interpolation; Laboratories; Latches; Optimization; Power demand;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location
Shanghai
Print_ISBN
978-1-4244-5797-7
Type
conf
DOI
10.1109/ICSICT.2010.5667682
Filename
5667682
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