Author :
Rupp, T. ; Chaudhary, N. ; Dev, K. ; Fukuzaki, Y. ; Gambino, J. ; Ho, H. ; Iba, J. ; Ito, E. ; Kiewra, E. ; Kim, B. ; Maldei, M. ; Matsunaga, T. ; Ning, J. ; Rengarajan, R. ; Sudo, A. ; Takagawa, Yousuke ; Tobben, D. ; Weybright, M. ; Worth, G.K. ; Divaka
Author_Institution :
IBM Corp., Hopewell Junction, NY, USA
Abstract :
This report describes improvements in the trench DRAM technology for 0.15 /spl mu/m groundrule and beyond. The optimum cell layout is 8F/sup 2/ with a cell area of only 0.18 /spl mu/m/sup 2/ for a 0.15 /spl mu/m groundrule. High node capacitance and low node contact resistance are demonstrated for these small groundrules. By using a dual gate oxide and self-aligned support junctions, the different performance requirements of array and support devices can be met. These technology features and their extendibility are evaluated on a 256 Mb DRAM design.
Keywords :
DRAM chips; capacitance; cellular arrays; contact resistance; integrated circuit layout; isolation technology; 0.15 micron; 256 Mbit; cell area; dual gate oxide; extendibility; groundrule; node capacitance; node contact resistance; optimum cell layout; self-aligned support junctions; trench DRAM technology; Capacitance; Capacitors; Contact resistance; Etching; Lithography; Oxidation; Random access memory; Research and development; Resists; Silicon compounds;
