Title :
Rescheduling transformations for high level synthesis
Author :
Papachristou, Christos A.
Author_Institution :
Comput. Eng. & Sci. Dept., Case Western Reserve Univ., Cleveland, OH, USA
Abstract :
A new approach is presented to high-level synthesis with self-testability. The motivation for this work is the need to fill the void between the fields of high-level synthesis and design for testability. The approach is based on a new allocation algorithm that maps a scheduled data-flow representation of the behavior into a data-path structure that is testable, with no need for test hardware insertion. An important feature of the approach is the rescheduling of transformations to perform design space exploration, under area, delay, and testability constraints. A significant advantage of this method is that the testability design is well integrated into the framework of high-level synthesis at the behavior level
Keywords :
logic design; logic testing; allocation algorithm; area constraints; behavior level; behaviour representation mapping; delay constraints; design space exploration; high level synthesis fields; high level synthesis framework; high-level synthesis; scheduled data-flow; self-testability; test hardware insertion; testability constraints; testability design; testable data-path structure; transformation rescheduling; Built-in self-test; Circuit testing; Costs; Design for testability; Hardware; High level synthesis; Logic testing; Performance evaluation; Scheduling algorithm; Space exploration;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100463
