Low power nonlinear Min/Max filters implemented in the CMOS technology

A novel, binary-tree, asynchronous, nonlinear Min/Max filter is presented in the paper. In the proposed circuit an input signal (current in this case) is first sampled in the circular delay line, controlled by a multiphase clock (8 phases in this case). In the next stage particular samples are converted to 1-bit signals with delays proportional to the values of these samples. In the following step the delay times are compared in digital binary-tree structure. The circuit has been simulated in the TSMC CMOS 0.18 μm process. It offers a precision of 99.5% at data rate of 2.5 MSamples/s and energy consumption of 0.3-1 pJ per input.